U.S. Pat. No. 6,211,572 to Fjelstad et al entitled “Semiconductor Chip Package With Fan-In Leads” discusses a compliant semiconductor chip package with fan-in leads. The package contains a multiplicity of bond ribbons connected between the contacts of a semiconductor chip and corresponding terminals on a top surface of a compliant layer. The compliant layer provides stress/strain relief to the bond ribbons encountered during handling or affixing the assembly to an external substrate. The chip package also contains a dielectric layer adjacent to at least one end of the bond ribbons. The dielectric layer relieves mechanical stresses/strains associated with the thermal mismatch of assembly and substrate materials during thermal cycling. The assembly can be manufactured without the need for any bond wiring tools since the bond ribbons are patterned and formed during a standard photolithographic stage within the manufacturing process. The manufacturing process is also amenable to simultaneous assembly of a multiplicity of undiced chips on a wafer or simultaneous assembly of diced chips in a processing boat. The disclosure of U.S. Pat. No. 6,211,572 is incorporated herein in its entirety by reference.
Wafer level packaging is also discussed in the reference by Gonzales et al. entitled “An Analysis Of The Reliability Of A Wafer Level Package (WLP) Using A Silicone Under The Bump (SUB) Configuration” (IEEE, 2003 Electronic Components And Technology Conference, pages 857-863). As discussed in the Gonzales et al. reference, wafer level chip scale package (WL-CSP) reliability can be improved using a Silicone Under the Bump structure. The silicone bump absorbs the thermal deformation mismatch between the silicon wafer level package (WLP) and the FR4 printed circuit board.